CPU Instruction Set

Tables below specify the mnemonic, encoding, clock cycles, affected flags (ordered as znhc), and description. The timings assume a CPU clock frequency of 4.194304 MHz (or 8.4 MHz for CGB in double speed mode), called “T-states”. Because all Game Boy timings are divisible by 4, many people specify timings and clock frequency divided by 4, called “M-cycles”.

8-bit Load instructions

MnemonicEncodingClock cyclesFlagsDescription
ld r,rxx4––r=r
ld r,nxx nn8––r=n
ld r,(HL)xx8––r=(HL)
ld (HL),r7x8––(HL)=r
ld (HL),n36 nn12––(HL)=n
ld A,(BC)0A8––A=(BC)
ld A,(DE)1A8––A=(DE)
ld A,(nn)FA16––A=(nn)
ld (BC),A028––(BC)=A
ld (DE),A128––(DE)=A
ld (nn),AEA16––(nn)=A
ld A,(FF00+n)F0 nn12––read from io-port n (memory FF00+n)
ld (FF00+n),AE0 nn12––write to io-port n (memory FF00+n)
ld A,(FF00+C)F28––read from io-port C (memory FF00+C)
ld (FF00+C),AE28––write to io-port C (memory FF00+C)
ldi (HL),A228––(HL)=A, HL=HL+1
ldi A,(HL)2A8––A=(HL), HL=HL+1
ldd (HL),A328––(HL)=A, HL=HL-1
ldd A,(HL)3A8––A=(HL), HL=HL-1

16-bit Load instructions

MnemonicEncodingClock cyclesFlagsDescription
ld rr,nnx1 nn nn12––rr=nn (rr may be BC,DE,HL or SP)
ld (nn),SP08 nn nn20––(nn)=SP
ld SP,HLF98––SP=HL
push rrx516––SP=SP-2 (SP)=rr ; rr may be BC,DE,HL,AF
pop rrx112(AF)rr=(SP) SP=SP+2 ; rr may be BC,DE,HL,AF

8-bit Arithmetic/Logic instructions

MnemonicEncodingClock cyclesFlagsDescription
add A,r8x4z0hcA=A+r
add A,nC6 nn8z0hcA=A+n
add A,(HL)868z0hcA=A+(HL)
adc A,r8x4z0hcA=A+r+cy
adc A,nCE nn8z0hcA=A+n+cy
adc A,(HL)8E8z0hcA=A+(HL)+cy
sub r9x4z1hcA=A-r
sub nD6 nn8z1hcA=A-n
sub (HL)968z1hcA=A-(HL)
sbc A,r9x4z1hcA=A-r-cy
sbc A,nDE nn8z1hcA=A-n-cy
sbc A,(HL)9E8z1hcA=A-(HL)-cy
and rAx4z010A=A & r
and nE6 nn8z010A=A & n
and (HL)A68z010A=A & (HL)
xor rAx4z000A=A xor r
xor nEE nn8z000A=A xor n
xor (HL)AE8z000A=A xor (HL)
or rBx4z000A=A | r
or nF6 nn8z000A=A | n
or (HL)B68z000A=A | (HL)
cp rBx4z1hccompare A-r
cp nFE nn8z1hccompare A-n
cp (HL)BE8z1hccompare A-(HL)
inc rxx4z0h-r=r+1
inc (HL)3412z0h-(HL)=(HL)+1
dec rxx4z1h-r=r-1
dec (HL)3512z1h-(HL)=(HL)-1
daa274z-0cdecimal adjust A
cpl2F4-11-A = A xor FF

16-bit Arithmetic/Logic instructions

MnemonicEncodingClock cyclesFlagsDescription
add HL,rrx98-0hcHL = HL+rr ; rr may be BC,DE,HL,SP
inc rrx38––rr = rr+1 ; rr may be BC,DE,HL,SP
dec rrxB8––rr = rr-1 ; rr may be BC,DE,HL,SP
add SP,ddE8 dd1600hcSP = SP +/- dd ; dd is 8-bit signed number
ld HL,SP+ddF8 dd1200hcHL = SP +/- dd ; dd is 8-bit signed number

Rotate and Shift instructions

MnemonicEncodingClock cyclesFlagsDescription
rlca074000crotate A left
rla174000crotate A left through carry
rrca0F4000crotate A right
rra1F4000crotate A right through carry
rlc rCB 0x8z00crotate left
rlc (HL)CB 0616z00crotate left
rl rCB 1x8z00crotate left through carry
rl (HL)CB 1616z00crotate left through carry
rrc rCB 0x8z00crotate right
rrc (HL)CB 0E16z00crotate right
rr rCB 1x8z00crotate right through carry
rr (HL)CB 1E16z00crotate right through carry
sla rCB 2x8z00cshift left arithmetic (b0=0)
sla (HL)CB 2616z00cshift left arithmetic (b0=0)
swap rCB 3x8z000exchange low/hi-nibble
swap (HL)CB 3616z000exchange low/hi-nibble
sra rCB 2x8z00cshift right arithmetic (b7=b7)
sra (HL)CB 2E16z00cshift right arithmetic (b7=b7)
srl rCB 3x8z00cshift right logical (b7=0)
srl (HL)CB 3E16z00cshift right logical (b7=0)

Single-bit Operation instructions

MnemonicEncodingClock cyclesFlagsDescription
bit n,rCB xx8z01-test bit n
bit n,(HL)CB xx12z01-test bit n
set n,rCB xx8––set bit n
set n,(HL)CB xx16––set bit n
res n,rCB xx8––reset bit n
res n,(HL)CB xx16––reset bit n

CPU Control instructions

MnemonicEncodingClock cyclesFlagsDescription
ccf3F4-00ccy=cy xor 1
nop004––no operation
halt76N*4––halt until interrupt occurs (low power)
stop10 00?––low power standby mode (VERY low power)
diF34––disable interrupts, IME=0
eiFB4––enable interrupts, IME=1

Jump instructions

MnemonicEncodingClock cyclesFlagsDescription
jp nnC3 nn nn16––jump to nn, PC=nn
jp HLE94––jump to HL, PC=HL
jp f,nnxx nn nn16/12––conditional jump if nz,z,nc,c
jr PC+dd18 dd12––relative jump to nn (PC=PC+8-bit signed)
jr f,PC+ddxx dd12/8––conditional relative jump if nz,z,nc,c
call nnCD nn nn24––call to nn, SP=SP-2, (SP)=PC, PC=nn
call f,nnxx nn nn24/12––conditional call if nz,z,nc,c
retC916––return, PC=(SP), SP=SP+2
ret fxx20/8––conditional return if nz,z,nc,c
retiD916––return and enable interrupts (IME=1)
rst nxx16––call to 00,08,10,18,20,28,30,38