If you are looking for textual explanations of what each each instruction does, please read gbz80(7); if you want a compact reference card/cheat sheet of each opcode and its flag effects, please consult the optables (whose octal view makes most encoding patterns more apparent).
The Game Boy’s SM83 processor possesses a CISC, variable-length instruction set.
This page attempts to shed some light on how the CPU decodes the raw bytes fed into it into instructions.
The first byte of each instruction is typically called the “opcode” (for “operation code”).
By noticing that some instructions perform identical operations but with different parameters, they can be grouped together; for example, inc bc, inc de, inc hl, and inc sp differ only in what 16-bit register they modify.
In each table, one line represents one such grouping.
Since many groupings have some variation, the variation has to be encoded in the instruction; for example, the above four instructions will be collectively referred to as inc r16.
Here are the possible placeholders and their values:
0
1
2
3
4
5
6
7
r8
b
c
d
e
h
l
[hl]
a
r16
bc
de
hl
sp
r16stk
bc
de
hl
af
r16mem
bc
de
hl+
hl-
cond
nz
z
nc
c
b3
A 3-bit bit index
tgt3
rst's target address, divided by 8
imm8
The following byte
imm16
The following two bytes, in little-endian order
These last two are a little special: if they are present in the instruction’s mnemonic, it means that the instruction is 1 (imm8) / 2 (imm16) extra bytes long.
[hl+] and [hl-] can also be notated [hli] and [hld] respectively (as in increment and decrement).
Groupings have been loosely associated based on what they do into separate tables; those have no particular ordering, and are purely for readability and convenience.
Finally, the instruction “families” have been further grouped into four “blocks”, differentiated by the first two bits of the opcode.